Course Report
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Course Features
Duration
3.2 hours
Delivery Method
Online
Available on
Limited Access
Accessibility
Desktop, Laptop
Language
English
Subtitles
English
Level
Intermediate
Teaching Type
Self Paced
Video Content
3.2 hours
Course Description
Course Overview
International Faculty
Post Course Interactions
Hands-On Training,Instructor-Moderated Discussions
Skills You Will Gain
What You Will Learn
Learn to build a pulse width modulation circuit using Verilog HDL and a Papilio Duo
Learn to map the physical I/O of an FPGA device to an FPGA board I/O using constraint files
Survey the history of FPGAs, how they're used, and some pitfalls to avoid
The course requires learners to purchase a low cost Papilio Pro FPGA development board
Understand how to install and setup a Xilinx ISE for a specific FPGA board
Understand the basic FPGA design process and the FPGA development environment
