Course Features
Duration
4 months
Delivery Method
Online
Available on
Limited Access
Accessibility
Desktop, Laptop
Language
English
Subtitles
English
Level
Intermediate
Effort
6 hours per week
Teaching Type
Self Paced
Course Description
Course Overview
Virtual Labs
International Faculty
Post Course Interactions
Instructor-Moderated Discussions
Case Studies, Captstone Projects
Skills You Will Gain
What You Will Learn
Apply hierarchical design methods to create bigger designs in VHDL or Verilog
Understand and practice all aspects of FPGA development, including conception, design, implementation, and debugging
Understand the rationale for each phase of the hardware development flow, including fitting, timing constraints, simulation, and programming
Create in the FPGA a working system on a chip design with Nios II soft processor, RAM and FLASH memory, and several peripherals