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FPGA Design for Embedded Systems Specialization

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Course Features

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Duration

4 months

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Delivery Method

Online

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Available on

Limited Access

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Accessibility

Desktop, Laptop

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Language

English

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Subtitles

English

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Level

Intermediate

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Effort

6 hours per week

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Teaching Type

Self Paced

Course Description

This course aims to teach you how to use Field Programmable Gate Arrays (FPGAs) in order create prototypes and products for a wide range of applications. FPGA design is a complicated topic. We will explain it so that even the most experienced designers can understand the basics. We will discuss the capabilities, trends and complexity of Field Programmable Gate Arrays and Complex Programmable Logic Devices. We will practice our skills in conception, design, implementation, debugging, and more. We will be able to learn about embedded IP and the processor cores. This includes tradeoffs between implementing IP or acquiring IP. The latest software and FPGA tools will be used to develop projects that provide a broad view of the capabilities of different Programmable SoC solutions. Topics include Verilog, VHDL and RTL Design for FPGA or CPLD Architectures FPGA Development Tools flow: specifying, synthesize and simulate, compile and program, debug Configurable embedded CPUs and embedded software Use soft-core and harder-core processors as well as OS options FPGA System Engineering, software-hardware Integration, testing IP development, and incorporating third-party IP. The capstone course will allow the learner to apply the concepts by building FPGA systems based upon low-cost evaluation boards

Course Overview

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Virtual Labs

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International Faculty

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Post Course Interactions

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Instructor-Moderated Discussions

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Case Studies, Captstone Projects

Skills You Will Gain

What You Will Learn

Apply hierarchical design methods to create bigger designs in VHDL or Verilog

Understand and practice all aspects of FPGA development, including conception, design, implementation, and debugging

Understand the rationale for each phase of the hardware development flow, including fitting, timing constraints, simulation, and programming

Create in the FPGA a working system on a chip design with Nios II soft processor, RAM and FLASH memory, and several peripherals

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